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Beyond Innovation Technology Co., Ltd.
BIT3715
BIT3715
High Performance PWM Controller
Preliminary Version: 0.00
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Please read the notice stated in this preamble carefully before accessing any contents of the document attached. Admission of BiTEK's statement therein is presumed once the document is released to the receiver.
BiTEK
December 20, 2005
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Preliminary
Confidential, for authorized user only
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Beyond Innovation Technology Co., Ltd.
BIT3715
Notice: Firstly, the information furnished by Beyond Innovation Technology Co. Ltd. (BiTEK) in this document is believed to be accurate and reliable and subject to BiTEK's amendment without prior notice. And the aforesaid information does not form any part or parts of any quotation or contract between BiTEK and the information receiver. Further, no responsibility is assumed for the usage of the aforesaid information. BiTEK makes no representation that the interconnect of its circuits as described herein will not infringe on exiting or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith. Besides, the product in this document is not designed for use in life support appliances, devices, or systems where malfunction of this product can reasonably be expected to result in personal injury. BiTEK customers' using or selling this product for use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale. At last, the information furnished in this document is the property of BiTEK and shall be treated as highly confidentiality; any kind of distribution, disclosure, copying, transformation or use of whole or parts of this document without duly authorization from BiTEK by prior written consent is strictly prohibited. The receiver shall fully compensate BiTEK without any reservation for any losses thereof due to its violation of BiTEK's confidential request. The receiver is deemed to agree on BiTEK's confidential request therein suppose that said receiver receives this document without making any expressly opposition. In the condition that aforesaid opposition is made, the receiver shall return this document to BiTEK immediately without any delay. -Version A4
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Beyond Innovation Technology Co., Ltd.
BIT3715
Pin Layout:
INN CMP LOAD CTOSC TIMER ONOFF GND OUT2 8 9 1 16 MODSEL ISEN OUTADJ PWMDC CTPWM PWMOUT VDD OUT1
Features:
Near Zero Stand By Current 4.5V ~ 8.0V operation Fixed High Frequency, Voltage Mode PWM Control Topology Latched Off Protection Build-In 2nd Low Frequency PWM Generator Build-In UVLO Low Power CMOS Process Totem Pole Output 16 Pin Package
General Description:
BIT3715 integrated circuit provides the essential PWM features for DC/DC conversion purpose in a small low cost 16-pin package. Another built-in low frequency PWM generator provides user more flexible applications. BIT3715 provides latched off protection feature may make the system more reliable. CMOS process makes BIT3715 consumes less power while comparing to conventional bipolar products.
Recommended Operating Condition:
Supply Voltage..................................4.5 ~ 8.0V Operating Ambient Temperature............-20 ~ 85 Operating Frequency..........................50K ~ 400K Hz
Functional Block Diagram:
MODSEL PWMDC CTPWM PWMOUT
OUTADJ LOAD
ISEN
2.5V
Latch Low Frequency PWM Generator
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60uA
1.0V CLOCK_L PRT CLOCK_L Adaptive Adjust CLOCK_H
-
INI
Protection Circuit
ERR_AMP UVLO Disable CMP_PWM
+ -
INN
1.25V CMP
LOAD Ramp Wave TIMER Clock & Ramp Wave CLOCK_H INI PRT
CTOSC
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Preliminary
+
OUT1
Digital Control Circuit
OUT2
TIMER ON/OFF
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BIT3715
Pin Description:
Table 1 Pin No. 1 2 3 4 Symbol INN CMP LOAD CTOSC I/O I O I/O I/O Descriptions The inverting input of the error amplifier. Output of the error amplifier. A switch that connected to the high frequency triangle wave generator. This switch is open while the voltage level of ISEN pin is lower than 1.3V. An external resistor connected here may change the operation frequency of CTOSC in open load situation. An external capacitor connected here decides the frequency of high frequency PWM controller. With internal reference current and an external capacitor connected here, it decides the required period of starting and the timing of initialization. The controller is forced to the reset mode while the voltage level of TIMER is lower than 0.3V. During reset mode, the current about 60uA will flow into the INN pin to reduce the output level of the error amplifier CMP to turn off the controller. The protection function will be enabled after this node is charged to exceed 2.5V. The output current of this pin is 20uA when the level of TIMER is lower than 0.3V. The output current becomes 1uA when the level of TIMER is higher than 0.3V The control pin of turning on or off the IC. 1V threshold with an internal 80K 15% ohm pull-low resistor. The ground pin of the device. The active high output driver. The active low output driver.
5
TIMER
I/O
6 7 8 9 10 11 12 13
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ONOFF GND OUT1 OUT2 VDD PWMOUT CTPWM PWMDC OUTADJ ISEN MODSEL
I I/O O O I
14 15 16
The power supplies pin of the device. The output pin of low frequency PWM generator. A 2.5V or floating two state O output is provided through this pin. The internal circuit limits the max. Duty-cycle to about 92%. With the internal reference current and an external capacitor connected here I/O can set the operation frequency of low frequency PWM generator with 1.0V ~ 2.5V triangle wave output. Low frequency PWM controlling input. A PWM output comes out by I comparing this DC input and the 1.0 ~ 2.5V triangle wave that is generated by CTPWM. Output regulation and protection. If a > 2.0 V voltage is detected. A ~ 60uA I current will flow into the INN pin to adjust the output of the error amplifier pin CMP to regulate the output voltage. Load current detection pin, the open load situation is detected if a less than I 1.3V input is sensed. O To set the output polarity of the low frequency PWM generator.

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BIT3715
The 1st Latched Off Protection: The ISEN pin may be
used for detecting if the operation is controlled stably during normal operation. For most of the applications, to define a "staring period" in which period no power deliver to the load side, are necessary. BIT3715 disable the latched off function when TIMER pin voltage < 2.5V. If "TIMER >2.5V and ISEN < 1.3V" for 32 cycles of the 2nd low frequency PWM, BIT3715 will shut down the output pins, OUT1 and OUT2 until the system is powered on again. The detail is as bellow: During TIMER > 2.5V, the system operates normally when the ISEN > or < than 1.3V. The lathed off function performs when ISEN has continuously been kept < 1.3V for 32 cycles of the 2nd low frequency PWM.
Functional Description:
The Power On Initialization: BIT3715 is in an "initial
state" when TIMER pin voltage is less than 0.3V. An internal current source charges the external capacitor connected on TIMER pin determines the operation timing of BIT3715. This current provides about 20uA when TIMER pin voltage is less than 0.3V, or about 1uA when TIMER pin voltage is large than 0.3V. Table 2 lists the states of each key features during TIMER pin voltage is less than 0.3V. Table 2 BIT3715 initial states Pin Number 4 8 9 11 12 Pin Name CTOSC OUT1 OUT2 PWMOUT CTPWM Status Normally run Forced to GND level Forced to VDD level Floating Normally run
The Output Adjustment and 2nd Latched Off Protection: The OUTADJ pin may be used for
detecting if the PWM control system operates normally. An about 60uA current source will charge the INN pin to adjust the output of CMP while OUTADJ > 2.0V. The latched off abnormal protection performs while TIMER > 2.5V. If "TIMER > 2.5V and OUTADJ > 2.0V" for 32 cycles of the 1st high frequency PWM, BIT3715 will shut down the output pins, OUT1 and OUT2, until the system is powered on again. The detail is as bellow: During TIMER > 2.5V, the system operates normally when the OUTADJ > or < than 2.0V. The lathed off function performs when OUTADJ has continuously been kept > 2.0V for 32 cycles of the 1st high frequency PWM. Or, a pulse signal on OUTADJ pin with > 50KHz which may > 2.0V or < 2.0V. BIT3715 performs latched off function when TIMER > 2.5V and the pulse signal has continuously present on OUTADJ pin for 32 cycles of the 1st high frequency PWM.
To Set the Operation Frequency of the 1st High Frequency PWM Controller: An external capacitor
CCTOSC pin CTOSC determines the frequency as equation (1) The frequency of the 1st high frequency PWM controller is:
FHFPWM =
K HF , K HF = 8.2e - 5 ............(1) CCTOSC
Or a 100KHz operation PWM control system if an 820pF capacitor is connected to pin CTOSC. Equation (1) is valid only when VDD=6V, temperature=30C and frequency (80K ~ 120K)Hz. Fig. 1 shows the relationship between the frequency of the high frequency www..com PWM and CTOSC capacitance.
CTOSC VS. Frequency 250.00 200.00 Frequency(KHz) 150.00 100.00 50.00 0.00 300 500 700 900 CTOSC(pF) 1100 1300 1500
To Set The Frequency Deviation of High Frequency PWM During Different Loading Condition: A
connected between GND and LOAD resistor may increase the operation frequency of CTOSC. An internal switch of the LOAD pin is closed may be used to change the frequency of CTOSC before ISEN had been triggered to larger than 1.3V. In many cases, the resonance frequency of the load is varied while the load is changed. For obtaining the better performance, the operation frequency of the PWM controller must fit to the resonance frequency of the load. The following diagram shows how the load resistance changes the 100KHz operation frequency of CTOSC pin. In above case, CTOSC is BiTEK connected by an 820pF capacitor. The normal operation frequency of high frequency PWM is 100KHz. If a December 20, 2005 different frequency says Fn is the set for normal operation. In BIT3715, the internal switch of the LOAD pin is `frozen" DCC CONTROLLED to "open" status when the ISEN > 1.3V.
Fig.1
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LOAD Resistor VS. CTOSC Frequency Deviation 200.00 175.00 CTOSC Frequency Deviation (KHz) 150.00 125.00 100.00 75.00 50.00 25.00 0.00 0 20 40 60 80 100 LOAD Resisor (Kohm) 173.30 151.10 126.50 108.70 91.40 76.20 CTOSC=100KHz 63.50 54.40 45.70 38.70 32.10
BIT3715
Setting the Frequency of the 2nd Low Frequency PWM Generator: A 2nd internal trimmed low frequency
oscillator generates a 3% accurate frequency on CTPWM pin with external capacitors. The capacitor values versus operation frequencies are as bellow: Note: Above equation (3) is valid only when operating frequency is between 150Hz ~ 1.5KHz The logic high output of pin PWMOUT is made by a 2.5V DC voltage and the floating state makes the logic low
FLFPWM =
26.80
4512 .............(3) [CCTPWM + 0.005] nF
portion. MODSEL pin provides the polarity selection of LF_PWM generator. If MODSEL pin is 0V, a 0% duty cycle is obtained when PWMDC < 1.0V. If this pin is pulled to IC VDD level, 0% duty cycle is obtained while PWMDC> 2.5V. Note: BIT3715 limits the maximum duty cycle to about 92 %. PWMOUT sends the pulses when ISEN >1.3V or TIMER >2.5V.
Fig.2
Then the frequency deviation can be calculated as Equation (2)
F100KHz x Fn .............(2) Fn = 100KHz
UVLO: The under-voltage-lockout circuit turns the output
driver off when supply voltage drops too low. Whole system includes the protection and timing circuits are reset (pin TIMER =0) in low VDD state.
DC/AC Characteristics:
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Absolute Ratings:
Table 3
Parameter Supply Voltage Ground Input pin Voltage Operating Ambit Temperature Operating Junction Temperature Storage Temperature
Symbol Ratings VDD -0.3~+ 8.8 GND 0.3 -0.3~ VDD+0.3 Ta -20 ~ +85 +150 -55~+150
Unit V V V C C C
Remarks Ta=25C

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Beyond Innovation Technology Co., Ltd. DC/AC Characteristics
Table 4
BIT3715
Test Conditions Min.
4.0 4 1.2125 1.25 2 4.0 0.2 1.2875 20 4.2 0.3 400 2.25 0.5 3 80 1.5 20 1 0.3 2.5 1.3 20 2.0 20 60 2.5 1.0 100K 1.0 2.5 2.5 Floating
Parameter
Supply Voltages Pin VDD input
Typ.
Max.
8.0
Unit
V mA V mV V V KHz V V V dB MHz uA uA V V V mV V mV uA V V Hz V V V
8V Supply Voltage Chip Consumed Current Ta=25C Error Amplifier Reference Voltage Non-Inverting input of the error Measure INN amplifier Line regulation VDD=4.0~8.0 V Under Voltage Look Out
Ta=25C Positive Going Threshold 3.8 Note3 Hysteresis 0.1 The 1st High Frequency Ramp Wave Generator Operating Frequency 50 Note1 Output peak(CTOSC) Output valley(CTOSC) Error Amplifier Input voltage 0.1 Note2 Open loop gain 60 Unit gain band width 1 Power On Initialization and Latched Off Protection Enable Pin TIMER Output current Case1. TIMER <0.3V Pin TIMER Output current VDD=6V, Ta=25C Case1. TIMER > 0.3V Power On Reset/Initialization Note 3 threshold on pin TIMER Latched Off Protection enable threshold on pin TIMER Load Detection Pin ISEN detection lower threshold VDD=6V, Ta=25C Hysterisis Output Detection and Adaptive Adjusting Pin OUTADJ detection lower threshold VDD=6V, Ta=25C Hysterisis www..com pin pull-up current source INN The 2nd Low Frequency PWM Generator Ramp Wave Peak(CTPWM) Ramp Wave Valley(CTPWM) PWM Frequency 10 Control voltage of 0 % Duty cycle on pin PWMDC Case 1. MODSEL = 0V Control voltage of 0 % Duty cycle VDD=6V, Ta=25C on pin PWMDC Case 1. MODSEL = ICVDD Output voltage of Pin PWMOUT for making the logic "high". Pin PWMOUT output for making the logic "low" Maximum Duty Cycle Output of the 1st PWM (OUT1, OUT2) CMOS output impedance (Note2, Note3) Rising Time VDD=6V, 2000pF(Note2, Falling Time Note3) Delay Time
92
B %
iTEK
50 Decemberohm2005 20, 110 nS 100 nS DCC CONTROLLED 600 nS
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BIT3715
Note 1. The output driver frequency is the half of the ramp wave frequency. Note 2. Only verified by simulation. Not 100% tested. Note 3. The voltages of the output driver OUT1 is pulled to GND and OUT2 is pulled to VDD in each off states. Timing Diagram The timing of the 2nd low frequency PWM generator, ISEN and LOAD pin are as bellow: A 51Kohm pulled-low resistor is connected on PWMOUT pin in this example.
CTPWM PWMDC >1.3V ISEN <1.3V >0.1 us PWMOUT(MODE="0")
PWMOUT(MODE="1")
LOAD
(SW close)
(SW open)
Fig. 3
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BIT3715 uses fixed frequency driving methodology. The power switch is driven by fixed frequency PWM controlled signal. The detail timing relationship is shown as bellow: The maximum duty cycle of OUT1 and OUT1 are smaller than 50% with 180phase difference.
Err_Amp Output Ramp Wave CMP_PWM Output
OUT1
OUT2

delay delay Fig. 4 delay
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BIT3715
Order Information:
BIT3715-SO
SO: SOP SS: SSOP Part number Beyond Innovation Technology Co., Ltd.
Soldering Information
Reflow Soldering:
The choice of heating method may be influenced by plastic QFP package). If infrared or vapor phase heating is used and the package is not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stenciling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferable be kept below 245 C for thick/large packages (packages with a thickness 2.5 mm or with a volume 350 mm3 so called thick/large packages). The top-surface temperature of the packages should preferable be kept below 260 C for thin/small packages (packages with a thickness < 2.5 mm and a volume < 350 mm3 so called thin/small packages). Stage 1'st Ram Up Rate Preheat 2'nd Ram Up Solder Joint Peak Temp www..com Ram Down rate Condition max3.0+/-2/sec 150~200 max3.0+/-2/sec 217 above 260 +0/-5 6/sec max Duration 60~180 sec 60~150 sec 20~40 sec -
Temp ()
260 217 200 150
25 RT
BiTEK
60~ 180 60~150
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Time(sec)
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Beyond Innovation Technology Co., Ltd. Wave Soldering:
BIT3715
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
Manual Soldering:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Package Information :
SOP type :
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BIT3715
SSOP type :
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